/*
utf-8
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单计时模块程序
一位计时、校时器，每clk上升沿计数
当校时触发时，不进行进位输出
------------------------------------------------
由刘丙旭出品
遵循署名-非商业性使用-相同方式共享 4.0 国际协议 (CC BY-NC-SA 4.0)
详情访问https://creativecommons.org/licenses/by-nc-sa/4.0/deed.zh
------------------------------------------------
*/

module timer(
clk,				//时钟输入
RESET,				//重置信号输入
data,				//预置数(在这里要设置为0)
SET,				//置数端(上升沿置数，在这里要设置为0)
en,					//使能端(1使能，0输出4'b1111)
a,					//最高计数(最高为9)
mode,				//计时、校时切换端(1计时，0校时)
c_in,				//进位输入
data_out,			//一位BCD输出
c_out				//进位输出
);

	input clk,RESET,SET,en,mode,c_in;
	input[3:0] data,a;
	output[3:0] data_out;
	output c_out;
	
	reg[3:0] data_out;
	reg c_out_tem = 0;
	reg c_out;

	reg[3:0] data_out_re;
	always @(posedge clk or posedge RESET)
	if(RESET == 1'b1)
		data_out_re <= 4'd0;
	else if(RESET == 1'b0 & SET == 1'b0)
		begin
			if(mode == 1'b1)
			begin
				if (c_in == 1'b1)
				begin
					if (data_out_re == a)
						begin 
							data_out_re <= 4'd0;
							c_out <= 1'b1;
						end
					else
						begin
							data_out_re <= data_out_re + 1;
							c_out <= 1'b0;
						end
				end
				else
					begin
						data_out_re <= data_out_re;
						c_out <= 1'b0;
					end
			end
			
			else if(mode == 1'b0)
			begin
				if(c_in == 1'b1)
				begin
					if (data_out_re == a)
						begin 
							data_out_re <= 4'd0;
							//c_out_tem <= ~c_out_tem;
						end
					else
						data_out_re <= data_out_re + 1;
				end
				else data_out_re <= data_out_re;
			end
		end
	
	else if(RESET == 1'b0 & SET == 1'b1)
		data_out_re <= data;
	
	
	always @(clk or en)
	if(en == 1'b1)
		data_out <= data_out_re;
	else if(en == 1'b0)
		data_out <= 4'b1111;
	


endmodule
